micro processor

The Multi Micro Processor (MµP) presents a scalable multi-processor architecture to be implemented on a single chip. The MµP architecture incorporates a configurable number of identical master processors, which are able to execute an extendable instruction set. Using a non-blocking instruction distribution network, the master processors are connected to a configurable set of shared co-processors for handling complex instructions unknown to the master processors. These co-processors are grouped in different types and may originate from libraries or are especially developed in accordance with the application domain. Based on a non-blocking result distribution network, any result generated by a co-processor is redirected back to the master processor that is executing the task which originally assigned the complex instruction. However, in case the corresponding task is not running anymore, the result is stored in a dedicated Register Cache that additionally enables quick task switches. A specialized co-processor is reserved for performing operations that are common operations of an Operating System kernel. Example operations for this hardware kernel are the assignment of runnable tasks to master processors, management of inter-task communication, handling of external events and transparent communication between different MµP chips. To complete the MµP architecture, a configurable memory controller is incorporated for connecting a multi-ported data cache, various instruction caches, the dedicated Register Cache and some of the co-processors to the external memory.